Commit 02b182e6 authored by Athira Rajeev's avatar Athira Rajeev Committed by Michael Ellerman
Browse files

powerpc/perf: Refactor the code definition of perf reg extended mask 



PERF_REG_PMU_MASK_300 and PERF_REG_PMU_MASK_31 defines the mask
value for extended registers. Current definition of these mask values
uses hex constant and does not use registers by name, making it less
readable. Patch refactor the macro values by or'ing together the actual
register value constants. Also include PERF_REG_EXTENDED_MAX as
part of enum definition.

Suggested-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: default avatarKajol <Jain&lt;kjain@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211007065505.27809-2-atrajeev@linux.vnet.ibm.com
parent f9473a65

arch/powerpc/include/uapi/asm/perf_regs.h

+13 −8
Original line number Diff line number Diff line
@@ -61,27 +61,32 @@ enum perf_event_powerpc_regs { 
	PERF_REG_POWERPC_PMC4,

	PERF_REG_POWERPC_PMC5,

	PERF_REG_POWERPC_PMC6,

	/* Max regs without the extended regs */

	/* Max mask value for interrupt regs w/o extended regs */

	PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,

	/* Max mask value for interrupt regs including extended regs */

	PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_PMC6 + 1,

};



#define PERF_REG_PMU_MASK	((1ULL << PERF_REG_POWERPC_MAX) - 1)



/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */

#define	PERF_EXCLUDE_REG_EXT_300	(7ULL << PERF_REG_POWERPC_MMCR3)



/*

 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300

 * includes 9 SPRS from MMCR0 to PMC6 excluding the

 * unsupported SPRS in PERF_EXCLUDE_REG_EXT_300.

 * unsupported SPRS MMCR3, SIER2 and SIER3.

 */

#define PERF_REG_PMU_MASK_300   ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300)

#define PERF_REG_PMU_MASK_300	\

	((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \

	(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \

	(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \

	(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \

	(1ULL << PERF_REG_POWERPC_PMC6))



/*

 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31

 * includes 12 SPRs from MMCR0 to PMC6.

 */

#define PERF_REG_PMU_MASK_31   (0xfffULL << PERF_REG_POWERPC_MMCR0)

#define PERF_REG_PMU_MASK_31	\

	(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \

	(1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))



#define PERF_REG_EXTENDED_MAX  (PERF_REG_POWERPC_PMC6 + 1)

#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */