Commit 0294868f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/display: properly handling AGP aperture in vm setup



Take into account whether or not the AGP aperture is
enabled or not when calculating the system aperture.

Fixes white screens with DCN 3.1.4.

Based on a patch from Yifan Zhang <yifan1.zhang@amd.com>

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f081cd4c
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+28 −14
Original line number Diff line number Diff line
@@ -1185,9 +1185,25 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_

	memset(pa_config, 0, sizeof(*pa_config));

	logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
	agp_base = 0;
	agp_bot = adev->gmc.agp_start >> 24;
	agp_top = adev->gmc.agp_end >> 24;

	/* AGP aperture is disabled */
	if (agp_bot == agp_top) {
		logical_addr_low  = adev->gmc.vram_start >> 18;
		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
			/*
			 * Raven2 has a HW issue that it is unable to use the vram which
			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
			 * workaround that increase system aperture high address (add 1)
			 * to get rid of the VM fault and hardware hang.
			 */
			logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
		else
			logical_addr_high = adev->gmc.vram_end >> 18;
	} else {
		logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
			/*
			 * Raven2 has a HW issue that it is unable to use the vram which
@@ -1198,11 +1214,9 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
			logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
		else
			logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
	}

	agp_base = 0;
	agp_bot = adev->gmc.agp_start >> 24;
	agp_top = adev->gmc.agp_end >> 24;

	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

	page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
	page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);