Commit 024b7b1d authored by Rajaravi Krishna Katta's avatar Rajaravi Krishna Katta Committed by Oded Gabbay
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habanalabs: Unify frequency set/get functionality 



Make the frequency set/get functionality common to all ASICs.
This makes more code reusable when adding support for newer ASICs.

Signed-off-by: default avatarRajaravi Krishna Katta <rkatta@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent f6fb3439

drivers/misc/habanalabs/common/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -11,4 +11,4 @@ HL_COMMON_FILES := common/habanalabs_drv.o common/device.o common/context.o \ 
		common/command_buffer.o common/hw_queue.o common/irq.o \

		common/sysfs.o common/hwmon.o common/memory.o \

		common/command_submission.o common/firmware_if.o \

		common/state_dump.o
 
		common/state_dump.o common/hwmgr.o

drivers/misc/habanalabs/common/habanalabs.h

+10 −0
Original line number Diff line number Diff line
@@ -456,6 +456,9 @@ struct hl_hints_range { 
 *                  for hints validity check.

 * device_dma_offset_for_host_access: the offset to add to host DMA addresses

 *                                    to enable the device to access them.

 * @max_freq_value: current max clk frequency.

 * @clk_pll_index: clock PLL index that specify which PLL determines the clock

 *                 we display to the user

 * @mmu_pgt_size: MMU page tables total size.

 * @mmu_pte_size: PTE size in MMU page tables.

 * @mmu_hop_table_size: MMU hop table size.
@@ -552,6 +555,8 @@ struct asic_fixed_properties { 
	u64				cb_va_end_addr;

	u64				dram_hints_align_mask;

	u64				device_dma_offset_for_host_access;

	u64				max_freq_value;

	u32				clk_pll_index;

	u32				mmu_pgt_size;

	u32				mmu_pte_size;

	u32				mmu_hop_table_size;
@@ -3006,6 +3011,11 @@ int hl_set_power(struct hl_device *hdev, 
			int sensor_index, u32 attr, long value);

int hl_get_power(struct hl_device *hdev,

			int sensor_index, u32 attr, long *value);

int hl_get_clk_rate(struct hl_device *hdev,

			u32 *cur_clk, u32 *max_clk);

void hl_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);

void hl_add_device_attr(struct hl_device *hdev,

			struct attribute_group *dev_attr_grp);

void hw_sob_get(struct hl_hw_sob *hw_sob);

void hw_sob_put(struct hl_hw_sob *hw_sob);

void hl_encaps_handle_do_release(struct kref *ref);

drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c→drivers/misc/habanalabs/common/hwmgr.c

+17 −21
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



/*

 * Copyright 2016-2018 HabanaLabs, Ltd.

 * Copyright 2019-2021 HabanaLabs, Ltd.

 * All Rights Reserved.

 */



#include "gaudiP.h"

#include "../include/gaudi/gaudi_fw_if.h"

#include "habanalabs.h"



void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)

void hl_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)

{

	struct gaudi_device *gaudi = hdev->asic_specific;



	if (freq == PLL_LAST)

		hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);

	hl_set_frequency(hdev, hdev->asic_prop.clk_pll_index,

			hdev->asic_prop.max_freq_value);

}



int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)

int hl_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk)

{

	long value;



	if (!hl_device_operational(hdev, NULL))

		return -ENODEV;



	value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);

	value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);



	if (value < 0) {

		dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n",
@@ -33,7 +30,7 @@ int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) 


	*max_clk = (value / 1000 / 1000);



	value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);

	value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);



	if (value < 0) {

		dev_err(hdev->dev,
@@ -51,15 +48,14 @@ static ssize_t clk_max_freq_mhz_show(struct device *dev, 
		struct device_attribute *attr, char *buf)

{

	struct hl_device *hdev = dev_get_drvdata(dev);

	struct gaudi_device *gaudi = hdev->asic_specific;

	long value;



	if (!hl_device_operational(hdev, NULL))

		return -ENODEV;



	value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, false);

	value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, false);



	gaudi->max_freq_value = value;

	hdev->asic_prop.max_freq_value = value;



	return sprintf(buf, "%lu\n", (value / 1000 / 1000));

}
@@ -68,7 +64,6 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev, 
		struct device_attribute *attr, const char *buf, size_t count)

{

	struct hl_device *hdev = dev_get_drvdata(dev);

	struct gaudi_device *gaudi = hdev->asic_specific;

	int rc;

	u64 value;
@@ -83,9 +78,10 @@ static ssize_t clk_max_freq_mhz_store(struct device *dev, 
		goto fail;

	}



	gaudi->max_freq_value = value * 1000 * 1000;

	hdev->asic_prop.max_freq_value = value * 1000 * 1000;



	hl_set_frequency(hdev, HL_GAUDI_MME_PLL, gaudi->max_freq_value);

	hl_set_frequency(hdev, hdev->asic_prop.clk_pll_index,

			hdev->asic_prop.max_freq_value);



fail:

	return count;
@@ -100,7 +96,7 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev, 
	if (!hl_device_operational(hdev, NULL))

		return -ENODEV;



	value = hl_get_frequency(hdev, HL_GAUDI_MME_PLL, true);

	value = hl_get_frequency(hdev, hdev->asic_prop.clk_pll_index, true);



	return sprintf(buf, "%lu\n", (value / 1000 / 1000));

}
@@ -108,14 +104,14 @@ static ssize_t clk_cur_freq_mhz_show(struct device *dev, 
static DEVICE_ATTR_RW(clk_max_freq_mhz);

static DEVICE_ATTR_RO(clk_cur_freq_mhz);



static struct attribute *gaudi_dev_attrs[] = {

static struct attribute *hl_dev_attrs[] = {

	&dev_attr_clk_max_freq_mhz.attr,

	&dev_attr_clk_cur_freq_mhz.attr,

	NULL,

};



void gaudi_add_device_attr(struct hl_device *hdev,

void hl_add_device_attr(struct hl_device *hdev,

			struct attribute_group *dev_attr_grp)

{

	dev_attr_grp->attrs = gaudi_dev_attrs;

	dev_attr_grp->attrs = hl_dev_attrs;

}

drivers/misc/habanalabs/gaudi/Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_hwmgr.o gaudi/gaudi_security.o \

HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_security.o \

	gaudi/gaudi_coresight.o

drivers/misc/habanalabs/gaudi/gaudi.c

+6 −5
Original line number Diff line number Diff line
@@ -661,6 +661,9 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev) 


	prop->server_type = HL_SERVER_TYPE_UNKNOWN;



	prop->clk_pll_index = HL_GAUDI_MME_PLL;

	prop->max_freq_value = GAUDI_MAX_CLK_FREQ;



	return 0;

}
@@ -1838,8 +1841,6 @@ static int gaudi_sw_init(struct hl_device *hdev) 


	gaudi->cpucp_info_get = gaudi_cpucp_info_get;



	gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ;



	hdev->asic_specific = gaudi;



	/* Create DMA pool for small allocations */
@@ -9444,9 +9445,9 @@ static const struct hl_asic_funcs gaudi_funcs = { 
	.debugfs_read64 = gaudi_debugfs_read64,

	.debugfs_write64 = gaudi_debugfs_write64,

	.debugfs_read_dma = gaudi_debugfs_read_dma,

	.add_device_attr = gaudi_add_device_attr,

	.add_device_attr = hl_add_device_attr,

	.handle_eqe = gaudi_handle_eqe,

	.set_pll_profile = gaudi_set_pll_profile,

	.set_pll_profile = hl_set_pll_profile,

	.get_events_stat = gaudi_get_events_stat,

	.read_pte = gaudi_read_pte,

	.write_pte = gaudi_write_pte,
@@ -9470,7 +9471,7 @@ static const struct hl_asic_funcs gaudi_funcs = { 
	.halt_coresight = gaudi_halt_coresight,

	.ctx_init = gaudi_ctx_init,

	.ctx_fini = gaudi_ctx_fini,

	.get_clk_rate = gaudi_get_clk_rate,

	.get_clk_rate = hl_get_clk_rate,

	.get_queue_id_for_cq = gaudi_get_queue_id_for_cq,

	.load_firmware_to_device = gaudi_load_firmware_to_device,

	.load_boot_fit_to_device = gaudi_load_boot_fit_to_device,