Commit 02485f4a authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
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arm64: dts: imx8mq-pico-pi: Align pin configuration group names with schema



Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent cf551b1f
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+6 −6
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@
		>;
	};

	pinctrl_pmic: pmicirq {
	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
		>;
@@ -335,7 +335,7 @@
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
@@ -351,7 +351,7 @@
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
@@ -367,7 +367,7 @@
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
		>;
@@ -385,7 +385,7 @@
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
@@ -397,7 +397,7 @@
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7