Commit 020d704c authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/urgent' into perf/core, to pick up dependency 



We are going to clean up perf's use of magic Intel model numbers,
so merge in the prerequisite commit that adds the model number
defines.

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents b8ab9220 970442c5

arch/x86/boot/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -162,6 +162,9 @@ isoimage: $(obj)/bzImage 
	for i in lib lib64 share end ; do \

		if [ -f /usr/$$i/syslinux/isolinux.bin ] ; then \

			cp /usr/$$i/syslinux/isolinux.bin $(obj)/isoimage ; \

			if [ -f /usr/$$i/syslinux/ldlinux.c32 ]; then \

				cp /usr/$$i/syslinux/ldlinux.c32 $(obj)/isoimage ; \

			fi ; \

			break ; \

		fi ; \

		if [ $$i = end ] ; then exit 1 ; fi ; \

arch/x86/include/asm/intel-family.h

0 → 100644
+68 −0
Original line number Diff line number Diff line 
#ifndef _ASM_X86_INTEL_FAMILY_H

#define _ASM_X86_INTEL_FAMILY_H



/*

 * "Big Core" Processors (Branded as Core, Xeon, etc...)

 *

 * The "_X" parts are generally the EP and EX Xeons, or the

 * "Extreme" ones, like Broadwell-E.

 *

 * Things ending in "2" are usually because we have no better

 * name for them.  There's no processor called "WESTMERE2".

 */



#define INTEL_FAM6_CORE_YONAH		0x0E

#define INTEL_FAM6_CORE2_MEROM		0x0F

#define INTEL_FAM6_CORE2_MEROM_L	0x16

#define INTEL_FAM6_CORE2_PENRYN		0x17

#define INTEL_FAM6_CORE2_DUNNINGTON	0x1D



#define INTEL_FAM6_NEHALEM		0x1E

#define INTEL_FAM6_NEHALEM_EP		0x1A

#define INTEL_FAM6_NEHALEM_EX		0x2E

#define INTEL_FAM6_WESTMERE		0x25

#define INTEL_FAM6_WESTMERE2		0x1F

#define INTEL_FAM6_WESTMERE_EP		0x2C

#define INTEL_FAM6_WESTMERE_EX		0x2F



#define INTEL_FAM6_SANDYBRIDGE		0x2A

#define INTEL_FAM6_SANDYBRIDGE_X	0x2D

#define INTEL_FAM6_IVYBRIDGE		0x3A

#define INTEL_FAM6_IVYBRIDGE_X		0x3E



#define INTEL_FAM6_HASWELL_CORE		0x3C

#define INTEL_FAM6_HASWELL_X		0x3F

#define INTEL_FAM6_HASWELL_ULT		0x45

#define INTEL_FAM6_HASWELL_GT3E		0x46



#define INTEL_FAM6_BROADWELL_CORE	0x3D

#define INTEL_FAM6_BROADWELL_XEON_D	0x56

#define INTEL_FAM6_BROADWELL_GT3E	0x47

#define INTEL_FAM6_BROADWELL_X		0x4F



#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E

#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E

#define INTEL_FAM6_SKYLAKE_X		0x55

#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E

#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E



/* "Small Core" Processors (Atom) */



#define INTEL_FAM6_ATOM_PINEVIEW	0x1C

#define INTEL_FAM6_ATOM_LINCROFT	0x26

#define INTEL_FAM6_ATOM_PENWELL		0x27

#define INTEL_FAM6_ATOM_CLOVERVIEW	0x35

#define INTEL_FAM6_ATOM_CEDARVIEW	0x36

#define INTEL_FAM6_ATOM_SILVERMONT1	0x37 /* BayTrail/BYT / Valleyview */

#define INTEL_FAM6_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */

#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* CherryTrail / Braswell */

#define INTEL_FAM6_ATOM_MERRIFIELD1	0x4A /* Tangier */

#define INTEL_FAM6_ATOM_MERRIFIELD2	0x5A /* Annidale */

#define INTEL_FAM6_ATOM_GOLDMONT	0x5C

#define INTEL_FAM6_ATOM_DENVERTON	0x5F /* Goldmont Microserver */



/* Xeon Phi */



#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */



#endif /* _ASM_X86_INTEL_FAMILY_H */

arch/x86/include/asm/msr.h

+2 −2
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ notrace static inline void native_write_msr(unsigned int msr, 
		     "2:\n"

		     _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)

		     : : "c" (msr), "a"(low), "d" (high) : "memory");

	if (msr_tracepoint_active(__tracepoint_read_msr))

	if (msr_tracepoint_active(__tracepoint_write_msr))

		do_trace_write_msr(msr, ((u64)high << 32 | low), 0);

}
@@ -141,7 +141,7 @@ notrace static inline int native_write_msr_safe(unsigned int msr, 
		     : "c" (msr), "0" (low), "d" (high),

		       [fault] "i" (-EIO)

		     : "memory");

	if (msr_tracepoint_active(__tracepoint_read_msr))

	if (msr_tracepoint_active(__tracepoint_write_msr))

		do_trace_write_msr(msr, ((u64)high << 32 | low), err);

	return err;

}