Commit 020c76d9 authored by Horatio Zhang's avatar Horatio Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add RAS POISON interrupt funcs for vcn_v4_0 



Add ras_poison_irq and functions. And fix the amdgpu_irq_put
call trace in vcn_v4_0_hw_fini.

[   44.563572] RIP: 0010:amdgpu_irq_put+0xa4/0xc0 [amdgpu]
[   44.563629] RSP: 0018:ffffb36740edfc90 EFLAGS: 00010246
[   44.563630] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000
[   44.563630] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
[   44.563631] RBP: ffffb36740edfcb0 R08: 0000000000000000 R09: 0000000000000000
[   44.563631] R10: 0000000000000000 R11: 0000000000000000 R12: ffff954c568e2ea8
[   44.563631] R13: 0000000000000000 R14: ffff954c568c0000 R15: ffff954c568e2ea8
[   44.563632] FS:  0000000000000000(0000) GS:ffff954f584c0000(0000) knlGS:0000000000000000
[   44.563632] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   44.563633] CR2: 00007f028741ba70 CR3: 000000026ca10000 CR4: 0000000000750ee0
[   44.563633] PKRU: 55555554
[   44.563633] Call Trace:
[   44.563634]  <TASK>
[   44.563634]  vcn_v4_0_hw_fini+0x62/0x160 [amdgpu]
[   44.563700]  vcn_v4_0_suspend+0x13/0x30 [amdgpu]
[   44.563755]  amdgpu_device_ip_suspend_phase2+0x240/0x470 [amdgpu]
[   44.563806]  amdgpu_device_ip_suspend+0x41/0x80 [amdgpu]
[   44.563858]  amdgpu_device_pre_asic_reset+0xd9/0x4a0 [amdgpu]
[   44.563909]  amdgpu_device_gpu_recover.cold+0x548/0xcf1 [amdgpu]
[   44.564006]  amdgpu_debugfs_reset_work+0x4c/0x80 [amdgpu]
[   44.564061]  process_one_work+0x21f/0x400
[   44.564062]  worker_thread+0x200/0x3f0
[   44.564063]  ? process_one_work+0x400/0x400
[   44.564064]  kthread+0xee/0x120
[   44.564065]  ? kthread_complete_and_exit+0x20/0x20
[   44.564066]  ret_from_fork+0x22/0x30

Suggested-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarHoratio Zhang <Hongkun.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6889f28c

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

+30 −6
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ static int vcn_v4_0_sw_init(void *handle) 


		/* VCN POISON TRAP */

		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],

				VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);

				VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);

		if (r)

			return r;
@@ -305,8 +305,8 @@ static int vcn_v4_0_hw_fini(void *handle) 
                        vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

			}

		}



		amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0);

		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))

			amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);

	}



	return 0;
@@ -1975,6 +1975,24 @@ static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgp 
	return 0;

}



/**

 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state

 *

 * @adev: amdgpu_device pointer

 * @source: interrupt sources

 * @type: interrupt types

 * @state: interrupt states

 *

 * Set VCN block RAS interrupt state

 */

static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,

	struct amdgpu_irq_src *source,

	unsigned int type,

	enum amdgpu_interrupt_state state)

{

	return 0;

}



/**

 * vcn_v4_0_process_interrupt - process VCN block interrupt

 *
@@ -2007,9 +2025,6 @@ static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_ 
	case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:

		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);

		break;

	case VCN_4_0__SRCID_UVD_POISON:

		amdgpu_vcn_process_poison_irq(adev, source, entry);

		break;

	default:

		DRM_ERROR("Unhandled interrupt: %d %d\n",

			  entry->src_id, entry->src_data[0]);
@@ -2024,6 +2039,11 @@ static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 
	.process = vcn_v4_0_process_interrupt,

};



static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {

	.set = vcn_v4_0_set_ras_interrupt_state,

	.process = amdgpu_vcn_process_poison_irq,

};



/**

 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions

 *
@@ -2041,6 +2061,9 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 


		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;

		adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;



		adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;

		adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;

	}

}
@@ -2114,6 +2137,7 @@ const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 
static struct amdgpu_vcn_ras vcn_v4_0_ras = {

	.ras_block = {

		.hw_ops = &vcn_v4_0_ras_hw_ops,

		.ras_late_init = amdgpu_vcn_ras_late_init,

	},

};