Commit 01c54e62 authored by Nava kishore Manne's avatar Nava kishore Manne Committed by Greg Kroah-Hartman
Browse files

fpga: versal-fpga: Add versal fpga manager driver 



Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Reviewed-by: default avatarMoritz Fischer <mdf@kernel.org>
Signed-off-by: default avatarAppana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: default avatarNava kishore Manne <nava.manne@xilinx.com>
Link: https://lore.kernel.org/r/20210626155248.5004-6-nava.manne@xilinx.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8c9b1301

drivers/fpga/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA 
	  to configure the programmable logic(PL) through PS

	  on ZynqMP SoC.



config FPGA_MGR_VERSAL_FPGA

	tristate "Xilinx Versal FPGA"

	depends on ARCH_ZYNQMP || COMPILE_TEST

	help

	  Select this option to enable FPGA manager driver support for

	  Xilinx Versal SoC. This driver uses the firmware interface to

	  configure the programmable logic(PL).



	  To compile this as a module, choose M here.

endif # FPGA

drivers/fpga/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o 
obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o

obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o

obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o

obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o

obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o

obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o

drivers/fpga/versal-fpga.c

0 → 100644
+96 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2019-2021 Xilinx, Inc.

 */



#include <linux/dma-mapping.h>

#include <linux/fpga/fpga-mgr.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/string.h>

#include <linux/firmware/xlnx-zynqmp.h>



static int versal_fpga_ops_write_init(struct fpga_manager *mgr,

				      struct fpga_image_info *info,

				      const char *buf, size_t size)

{

	return 0;

}



static int versal_fpga_ops_write(struct fpga_manager *mgr,

				 const char *buf, size_t size)

{

	dma_addr_t dma_addr = 0;

	char *kbuf;

	int ret;



	kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);

	if (!kbuf)

		return -ENOMEM;



	memcpy(kbuf, buf, size);

	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);

	dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);



	return ret;

}



static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,

					  struct fpga_image_info *info)

{

	return 0;

}



static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)

{

	return FPGA_MGR_STATE_UNKNOWN;

}



static const struct fpga_manager_ops versal_fpga_ops = {

	.state = versal_fpga_ops_state,

	.write_init = versal_fpga_ops_write_init,

	.write = versal_fpga_ops_write,

	.write_complete = versal_fpga_ops_write_complete,

};



static int versal_fpga_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct fpga_manager *mgr;

	int ret;



	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));

	if (ret < 0) {

		dev_err(dev, "no usable DMA configuration\n");

		return ret;

	}



	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",

				   &versal_fpga_ops, NULL);

	if (!mgr)

		return -ENOMEM;



	return devm_fpga_mgr_register(dev, mgr);

}



static const struct of_device_id versal_fpga_of_match[] = {

	{ .compatible = "xlnx,versal-fpga", },

	{},

};

MODULE_DEVICE_TABLE(of, versal_fpga_of_match);



static struct platform_driver versal_fpga_driver = {

	.probe = versal_fpga_probe,

	.driver = {

		.name = "versal_fpga_manager",

		.of_match_table = of_match_ptr(versal_fpga_of_match),

	},

};

module_platform_driver(versal_fpga_driver);



MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");

MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");

MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");

MODULE_LICENSE("GPL");