Commit 01c0c124 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32 



[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.

[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarDillon Varone <Dillon.Varone@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ea192af5

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -864,6 +864,7 @@ struct dc_debug_options { 
	bool enable_dp_dig_pixel_rate_div_policy;

	enum lttpr_mode lttpr_mode_override;

	unsigned int dsc_delay_factor_wa_x1000;

	unsigned int min_prefetch_in_strobe_ns;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -724,6 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.enable_dp_dig_pixel_rate_div_policy = 1,

	.allow_sw_cursor_fallback = false,

	.alloc_extra_way_for_cursor = true,

	.min_prefetch_in_strobe_ns = 60000, // 60us

};



static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -722,6 +722,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.enable_dp_dig_pixel_rate_div_policy = 1,

	.allow_sw_cursor_fallback = false,

	.alloc_extra_way_for_cursor = true,

	.min_prefetch_in_strobe_ns = 60000, // 60us

};



static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+2 −0
Original line number Diff line number Diff line
@@ -2351,6 +2351,8 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa 
	/* DML DSC delay factor workaround */

	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;



	dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;



	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */

	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+4 −0
Original line number Diff line number Diff line
@@ -786,6 +786,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
					v->SwathHeightY[k],

					v->SwathHeightC[k],

					TWait,

					v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?

							mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,

					/* Output */

					&v->DSTXAfterScaler[k],

					&v->DSTYAfterScaler[k],
@@ -3245,6 +3247,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
							v->swath_width_chroma_ub_this_state[k],

							v->SwathHeightYThisState[k],

							v->SwathHeightCThisState[k], v->TWait,

							v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?

									mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,



							/* Output */

							&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],