Commit 01b8f5b5 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Sebastian Reichel
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dt-bindings: reset: ocelot: Add Luton and Jaguar2 support 



This adds the support for 2 others MIPS based VCore III SoCs: Luton
and Jaguar2.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
parent 3650b228

Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

+3 −1
Original line number Diff line number Diff line
@@ -7,7 +7,9 @@ The reset registers are both present in the MSCC vcoreiii MIPS and 
microchip Sparx5 armv8 SoC's.



Required Properties:

 - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"



 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",

   "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"



Example:

	reset@1070008 {