Commit 017d6250 authored by Voon Weifeng's avatar Voon Weifeng Committed by David S. Miller
Browse files

stmmac: intel: Enable SERDES PHY rx clk for PSE 



EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up
sequence and vice versa.

Signed-off-by: default avatarVoon Weifeng <weifeng.voon@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 56f15e2c

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+10 −0
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) 
		return data;

	}



	/* PSE only - ungate SGMII PHY Rx Clock */

	if (intel_priv->is_pse)

		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,

			       0, SERDES_PHY_RX_CLK);



	return 0;

}
@@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) 


	serdes_phy_addr = intel_priv->mdio_adhoc_addr;



	/* PSE only - gate SGMII PHY Rx Clock */

	if (intel_priv->is_pse)

		mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,

			       SERDES_PHY_RX_CLK, 0);



	/*  move power state to P3 */

	data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 


/* SERDES defines */

#define SERDES_PLL_CLK		BIT(0)		/* PLL clk valid signal */

#define SERDES_PHY_RX_CLK	BIT(1)		/* PSE SGMII PHY rx clk */

#define SERDES_RST		BIT(2)		/* Serdes Reset */

#define SERDES_PWR_ST_MASK	GENMASK(6, 4)	/* Serdes Power state*/

#define SERDES_PWR_ST_SHIFT	4