Commit 015a89f0 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: add cpufreq support 



The change adds a description of a SM8450 cpufreq-epss controller and
references to it from CPU nodes.

Signed-off-by: default avatarVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215043440.605624-11-vkoul@kernel.org
parent 61eba74e

arch/arm64/boot/dts/qcom/sm8450.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
			next-level-cache = <&L2_0>;

			power-domains = <&CPU_PD0>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_0: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -61,6 +62,7 @@ 
			next-level-cache = <&L2_100>;

			power-domains = <&CPU_PD1>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_100: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -75,6 +77,7 @@ 
			next-level-cache = <&L2_200>;

			power-domains = <&CPU_PD2>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_200: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -89,6 +92,7 @@ 
			next-level-cache = <&L2_300>;

			power-domains = <&CPU_PD3>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 0>;

			L2_300: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -103,6 +107,7 @@ 
			next-level-cache = <&L2_400>;

			power-domains = <&CPU_PD4>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_400: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -117,6 +122,7 @@ 
			next-level-cache = <&L2_500>;

			power-domains = <&CPU_PD5>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_500: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -132,6 +138,7 @@ 
			next-level-cache = <&L2_600>;

			power-domains = <&CPU_PD6>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 1>;

			L2_600: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -146,6 +153,7 @@ 
			next-level-cache = <&L2_700>;

			power-domains = <&CPU_PD7>;

			power-domain-names = "psci";

			qcom,freq-domain = <&cpufreq_hw 2>;

			L2_700: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;
@@ -867,6 +875,21 @@ 
			};

		};



		cpufreq_hw: cpufreq@17d91000 {

			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";

			reg = <0 0x17d91000 0 0x1000>,

			      <0 0x17d92000 0 0x1000>,

			      <0 0x17d93000 0 0x1000>;

			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;

			clock-names = "xo", "alternate";

			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";

			#freq-domain-cells = <1>;

		};



		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";