Commit 014e79d7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

cpufreq: remove s3c24xx drivers 



All s3c24xx platforms were removed, so these five drivers are all
obsolete now.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent a7ddf74b

drivers/cpufreq/Kconfig.arm

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Original line number Diff line number Diff line
@@ -189,84 +189,6 @@ config ARM_RASPBERRYPI_CPUFREQ 


	  If in doubt, say N.



config ARM_S3C_CPUFREQ

	bool

	help

	  Internal configuration node for common cpufreq on Samsung SoC



config ARM_S3C24XX_CPUFREQ

	bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"

	depends on ARCH_S3C24XX

	select ARM_S3C_CPUFREQ

	help

	  This enables the CPUfreq driver for the Samsung S3C24XX family

	  of CPUs.



	  For details, take a look at <file:Documentation/cpu-freq>.



	  If in doubt, say N.



config ARM_S3C24XX_CPUFREQ_DEBUG

	bool "Debug CPUfreq Samsung driver core"

	depends on ARM_S3C24XX_CPUFREQ

	help

	  Enable s3c_freq_dbg for the Samsung S3C CPUfreq core



config ARM_S3C24XX_CPUFREQ_IODEBUG

	bool "Debug CPUfreq Samsung driver IO timing"

	depends on ARM_S3C24XX_CPUFREQ

	help

	  Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core



config ARM_S3C24XX_CPUFREQ_DEBUGFS

	bool "Export debugfs for CPUFreq"

	depends on ARM_S3C24XX_CPUFREQ && DEBUG_FS

	help

	  Export status information via debugfs.



config ARM_S3C2410_CPUFREQ

	bool

	depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2410

	help

	  CPU Frequency scaling support for S3C2410



config ARM_S3C2412_CPUFREQ

	bool

	depends on ARM_S3C24XX_CPUFREQ && CPU_S3C2412

	default y

	select S3C2412_IOTIMING

	help

	  CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.



config ARM_S3C2416_CPUFREQ

	bool "S3C2416 CPU Frequency scaling support"

	depends on CPU_S3C2416

	help

	  This adds the CPUFreq driver for the Samsung S3C2416 and

	  S3C2450 SoC. The S3C2416 supports changing the rate of the

	  armdiv clock source and also entering a so called dynamic

	  voltage scaling mode in which it is possible to reduce the

	  core voltage of the CPU.



	  If in doubt, say N.



config ARM_S3C2416_CPUFREQ_VCORESCALE

	bool "Allow voltage scaling for S3C2416 arm core"

	depends on ARM_S3C2416_CPUFREQ && REGULATOR

	help

	  Enable CPU voltage scaling when entering the dvs mode.

	  It uses information gathered through existing hardware and

	  tests but not documented in any datasheet.



	  If in doubt, say N.



config ARM_S3C2440_CPUFREQ

	bool "S3C2440/S3C2442 CPU Frequency scaling support"

	depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2440 || CPU_S3C2442)

	default y

	help

	  CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.



config ARM_S3C64XX_CPUFREQ

	bool "Samsung S3C64XX"

	depends on CPU_S3C6410

drivers/cpufreq/Makefile

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Original line number Diff line number Diff line
@@ -71,13 +71,7 @@ obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o 
obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)	+= qcom-cpufreq-hw.o

obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)	+= qcom-cpufreq-nvmem.o

obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) 	+= raspberrypi-cpufreq.o

obj-$(CONFIG_ARM_S3C2410_CPUFREQ)	+= s3c2410-cpufreq.o

obj-$(CONFIG_ARM_S3C2412_CPUFREQ)	+= s3c2412-cpufreq.o

obj-$(CONFIG_ARM_S3C2416_CPUFREQ)	+= s3c2416-cpufreq.o

obj-$(CONFIG_ARM_S3C2440_CPUFREQ)	+= s3c2440-cpufreq.o

obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o

obj-$(CONFIG_ARM_S3C24XX_CPUFREQ)	+= s3c24xx-cpufreq.o

obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o

obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o

obj-$(CONFIG_ARM_SA1110_CPUFREQ)	+= sa1110-cpufreq.o

obj-$(CONFIG_ARM_SCMI_CPUFREQ)		+= scmi-cpufreq.o

drivers/cpufreq/s3c2410-cpufreq.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2006-2008 Simtec Electronics

 *	http://armlinux.simtec.co.uk/

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * S3C2410 CPU Frequency scaling

*/



#include <linux/init.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/cpufreq.h>

#include <linux/device.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/soc/samsung/s3c-cpufreq-core.h>

#include <linux/soc/samsung/s3c-pm.h>



#include <asm/mach/arch.h>

#include <asm/mach/map.h>



#define S3C2410_CLKDIVN_PDIVN	     (1<<0)

#define S3C2410_CLKDIVN_HDIVN	     (1<<1)



/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */



static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)

{

	u32 clkdiv = 0;



	if (cfg->divs.h_divisor == 2)

		clkdiv |= S3C2410_CLKDIVN_HDIVN;



	if (cfg->divs.p_divisor != cfg->divs.h_divisor)

		clkdiv |= S3C2410_CLKDIVN_PDIVN;



	s3c24xx_write_clkdivn(clkdiv);

}



static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)

{

	unsigned long hclk, fclk, pclk;

	unsigned int hdiv, pdiv;

	unsigned long hclk_max;



	fclk = cfg->freq.fclk;

	hclk_max = cfg->max.hclk;



	cfg->freq.armclk = fclk;



	s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",

		      __func__, fclk, hclk_max);



	hdiv = (fclk > cfg->max.hclk) ? 2 : 1;

	hclk = fclk / hdiv;



	if (hclk > cfg->max.hclk) {

		s3c_freq_dbg("%s: hclk too big\n", __func__);

		return -EINVAL;

	}



	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;

	pclk = hclk / pdiv;



	if (pclk > cfg->max.pclk) {

		s3c_freq_dbg("%s: pclk too big\n", __func__);

		return -EINVAL;

	}



	pdiv *= hdiv;



	/* record the result */

	cfg->divs.p_divisor = pdiv;

	cfg->divs.h_divisor = hdiv;



	return 0;

}



static struct s3c_cpufreq_info s3c2410_cpufreq_info = {

	.max		= {

		.fclk	= 200000000,

		.hclk	= 100000000,

		.pclk	=  50000000,

	},



	/* transition latency is about 5ms worst-case, so

	 * set 10ms to be sure */

	.latency	= 10000000,



	.locktime_m	= 150,

	.locktime_u	= 150,

	.locktime_bits	= 12,



	.need_pll	= 1,



	.name		= "s3c2410",

	.calc_iotiming	= s3c2410_iotiming_calc,

	.set_iotiming	= s3c2410_iotiming_set,

	.get_iotiming	= s3c2410_iotiming_get,



	.set_fvco	= s3c2410_set_fvco,

	.set_refresh	= s3c2410_cpufreq_setrefresh,

	.set_divs	= s3c2410_cpufreq_setdivs,

	.calc_divs	= s3c2410_cpufreq_calcdivs,



	.debug_io_show	= s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),

};



static int s3c2410_cpufreq_add(struct device *dev,

			       struct subsys_interface *sif)

{

	return s3c_cpufreq_register(&s3c2410_cpufreq_info);

}



static struct subsys_interface s3c2410_cpufreq_interface = {

	.name		= "s3c2410_cpufreq",

	.subsys		= &s3c2410_subsys,

	.add_dev	= s3c2410_cpufreq_add,

};



static int __init s3c2410_cpufreq_init(void)

{

	return subsys_interface_register(&s3c2410_cpufreq_interface);

}

arch_initcall(s3c2410_cpufreq_init);



static int s3c2410a_cpufreq_add(struct device *dev,

				struct subsys_interface *sif)

{

	/* alter the maximum freq settings for S3C2410A. If a board knows

	 * it only has a maximum of 200, then it should register its own

	 * limits. */



	s3c2410_cpufreq_info.max.fclk = 266000000;

	s3c2410_cpufreq_info.max.hclk = 133000000;

	s3c2410_cpufreq_info.max.pclk =  66500000;

	s3c2410_cpufreq_info.name = "s3c2410a";



	return s3c2410_cpufreq_add(dev, sif);

}



static struct subsys_interface s3c2410a_cpufreq_interface = {

	.name		= "s3c2410a_cpufreq",

	.subsys		= &s3c2410a_subsys,

	.add_dev	= s3c2410a_cpufreq_add,

};



static int __init s3c2410a_cpufreq_init(void)

{

	return subsys_interface_register(&s3c2410a_cpufreq_interface);

}

arch_initcall(s3c2410a_cpufreq_init);

drivers/cpufreq/s3c2412-cpufreq.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright 2008 Simtec Electronics

 *	http://armlinux.simtec.co.uk/

 *	Ben Dooks <ben@simtec.co.uk>

 *

 * S3C2412 CPU Frequency scalling

*/



#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt



#include <linux/init.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/cpufreq.h>

#include <linux/device.h>

#include <linux/delay.h>

#include <linux/clk.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/soc/samsung/s3c-cpufreq-core.h>

#include <linux/soc/samsung/s3c-pm.h>



#include <asm/mach/arch.h>

#include <asm/mach/map.h>



#define S3C2412_CLKDIVN_PDIVN		(1<<2)

#define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)

#define S3C2412_CLKDIVN_ARMDIVN		(1<<3)

#define S3C2412_CLKDIVN_DVSEN		(1<<4)

#define S3C2412_CLKDIVN_HALFHCLK	(1<<5)

#define S3C2412_CLKDIVN_USB48DIV	(1<<6)

#define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)

#define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)

#define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)

#define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)

#define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)

#define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)



/* our clock resources. */

static struct clk *xtal;

static struct clk *fclk;

static struct clk *hclk;

static struct clk *armclk;



/* HDIV: 1, 2, 3, 4, 6, 8 */



static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)

{

	unsigned int hdiv, pdiv, armdiv, dvs;

	unsigned long hclk, fclk, armclk, armdiv_clk;

	unsigned long hclk_max;



	fclk = cfg->freq.fclk;

	armclk = cfg->freq.armclk;

	hclk_max = cfg->max.hclk;



	/* We can't run hclk above armclk as at the best we have to

	 * have armclk and hclk in dvs mode. */



	if (hclk_max > armclk)

		hclk_max = armclk;



	s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",

		     __func__, fclk, armclk, hclk_max);

	s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",

		     __func__, cfg->freq.fclk, cfg->freq.armclk,

		     cfg->freq.hclk, cfg->freq.pclk);



	armdiv = fclk / armclk;



	if (armdiv < 1)

		armdiv = 1;

	if (armdiv > 2)

		armdiv = 2;



	cfg->divs.arm_divisor = armdiv;

	armdiv_clk = fclk / armdiv;



	hdiv = armdiv_clk / hclk_max;

	if (hdiv < 1)

		hdiv = 1;



	cfg->freq.hclk = hclk = armdiv_clk / hdiv;



	/* set dvs depending on whether we reached armclk or not. */

	cfg->divs.dvs = dvs = armclk < armdiv_clk;



	/* update the actual armclk we achieved. */

	cfg->freq.armclk = dvs ? hclk : armdiv_clk;



	s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",

		     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);



	if (hdiv > 4)

		goto invalid;



	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;



	if ((hclk / pdiv) > cfg->max.pclk)

		pdiv++;



	cfg->freq.pclk = hclk / pdiv;



	s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);



	if (pdiv > 2)

		goto invalid;



	pdiv *= hdiv;



	/* store the result, and then return */



	cfg->divs.h_divisor = hdiv * armdiv;

	cfg->divs.p_divisor = pdiv * armdiv;



	return 0;



invalid:

	return -EINVAL;

}



static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)

{

	unsigned long clkdiv;

	unsigned long olddiv;



	olddiv = clkdiv = s3c24xx_read_clkdivn();



	/* clear off current clock info */



	clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;

	clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;

	clkdiv &= ~S3C2412_CLKDIVN_PDIVN;



	if (cfg->divs.arm_divisor == 2)

		clkdiv |= S3C2412_CLKDIVN_ARMDIVN;



	clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);



	if (cfg->divs.p_divisor != cfg->divs.h_divisor)

		clkdiv |= S3C2412_CLKDIVN_PDIVN;



	s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);

	s3c24xx_write_clkdivn(clkdiv);



	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);

}



/* set the default cpu frequency information, based on an 200MHz part

 * as we have no other way of detecting the speed rating in software.

 */



static struct s3c_cpufreq_info s3c2412_cpufreq_info = {

	.max		= {

		.fclk	= 200000000,

		.hclk	= 100000000,

		.pclk	=  50000000,

	},



	.latency	= 5000000, /* 5ms */



	.locktime_m	= 150,

	.locktime_u	= 150,

	.locktime_bits	= 16,



	.name		= "s3c2412",

	.set_refresh	= s3c2412_cpufreq_setrefresh,

	.set_divs	= s3c2412_cpufreq_setdivs,

	.calc_divs	= s3c2412_cpufreq_calcdivs,



	.calc_iotiming	= s3c2412_iotiming_calc,

	.set_iotiming	= s3c2412_iotiming_set,

	.get_iotiming	= s3c2412_iotiming_get,



	.debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),

};



static int s3c2412_cpufreq_add(struct device *dev,

			       struct subsys_interface *sif)

{

	unsigned long fclk_rate;



	hclk = clk_get(NULL, "hclk");

	if (IS_ERR(hclk)) {

		pr_err("cannot find hclk clock\n");

		return -ENOENT;

	}



	fclk = clk_get(NULL, "fclk");

	if (IS_ERR(fclk)) {

		pr_err("cannot find fclk clock\n");

		goto err_fclk;

	}



	fclk_rate = clk_get_rate(fclk);

	if (fclk_rate > 200000000) {

		pr_info("fclk %ld MHz, assuming 266MHz capable part\n",

			fclk_rate / 1000000);

		s3c2412_cpufreq_info.max.fclk = 266000000;

		s3c2412_cpufreq_info.max.hclk = 133000000;

		s3c2412_cpufreq_info.max.pclk =  66000000;

	}



	armclk = clk_get(NULL, "armclk");

	if (IS_ERR(armclk)) {

		pr_err("cannot find arm clock\n");

		goto err_armclk;

	}



	xtal = clk_get(NULL, "xtal");

	if (IS_ERR(xtal)) {

		pr_err("cannot find xtal clock\n");

		goto err_xtal;

	}



	return s3c_cpufreq_register(&s3c2412_cpufreq_info);



err_xtal:

	clk_put(armclk);

err_armclk:

	clk_put(fclk);

err_fclk:

	clk_put(hclk);



	return -ENOENT;

}



static struct subsys_interface s3c2412_cpufreq_interface = {

	.name		= "s3c2412_cpufreq",

	.subsys		= &s3c2412_subsys,

	.add_dev	= s3c2412_cpufreq_add,

};



static int s3c2412_cpufreq_init(void)

{

	return subsys_interface_register(&s3c2412_cpufreq_interface);

}

arch_initcall(s3c2412_cpufreq_init);

drivers/cpufreq/s3c2416-cpufreq.c

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