Commit 012e19f4 authored by Jonathan Albrieux's avatar Jonathan Albrieux Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: msm8916: Add blsp_i2c3 



MSM8916 has another I2C QUP controller that can be enabled on
GPIO 10 and 11.

Add blsp_i2c3 to msm8916.dtsi and disable it by default.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: default avatarStephan Gerhold <stephan@gerhold.net>
Signed-off-by: default avatarJonathan Albrieux <jonathan.albrieux@gmail.com>
Link: https://lore.kernel.org/r/20210125094435.7528-3-jonathan.albrieux@gmail.com


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent b3a6b088

arch/arm64/boot/dts/qcom/msm8916-pins.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -220,6 +220,22 @@ 
		bias-disable;

	};



	i2c3_default: i2c3-default {

		pins = "gpio10", "gpio11";

		function = "blsp_i2c3";



		drive-strength = <2>;

		bias-disable;

	};



	i2c3_sleep: i2c3-sleep {

		pins = "gpio10", "gpio11";

		function = "gpio";



		drive-strength = <2>;

		bias-disable;

	};



	i2c4_default: i2c4-default {

		pins = "gpio14", "gpio15";

		function = "blsp_i2c4";

arch/arm64/boot/dts/qcom/msm8916.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -1529,6 +1529,21 @@ 
			status = "disabled";

		};



		blsp_i2c3: i2c@78b7000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b7000 0x500>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&i2c3_default>;

			pinctrl-1 = <&i2c3_sleep>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		blsp_spi3: spi@78b7000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b7000 0x500>;