Commit 010299bf authored by Vinod Koul's avatar Vinod Koul
Browse files

Merge branch 'topic/dw' into for-linus

parents 466e601a 7b0c03ec

Documentation/devicetree/bindings/dma/snps-dma.txt

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@@ -27,6 +27,10 @@ Optional properties: 
  general purpose DMA channel allocator. False if not passed.

- multi-block: Multi block transfers supported by hardware. Array property with

  one cell per channel. 0: not supported, 1 (default): supported.

- snps,dma-protection-control: AHB HPROT[3:1] protection setting.

  The default value is 0 (for non-cacheable, non-buffered,

  unprivileged data access).

  Refer to include/dt-bindings/dma/dw-dmac.h for possible values.



Example:

MAINTAINERS

+3 −1
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@@ -14363,9 +14363,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER 
M:	Viresh Kumar <vireshk@kernel.org>

R:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

S:	Maintained

F:	Documentation/devicetree/bindings/dma/snps-dma.txt

F:	drivers/dma/dw/

F:	include/dt-bindings/dma/dw-dmac.h

F:	include/linux/dma/dw.h

F:	include/linux/platform_data/dma-dw.h

F:	drivers/dma/dw/



SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER

M:	Jose Abreu <Jose.Abreu@synopsys.com>

drivers/dma/dw/core.c

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@@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc) 


static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)

{

	struct dw_dma *dw = to_dw_dma(dwc->chan.device);

	u32 cfghi = DWC_CFGH_FIFO_MODE;

	u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);

	bool hs_polarity = dwc->dws.hs_polarity;



	cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);

	cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);

	cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);



	/* Set polarity of handshake interface */

	cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;

drivers/dma/dw/platform.c

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@@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *pdev) 
			pdata->multi_block[tmp] = 1;

	}



	if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {

		if (tmp > CHAN_PROTCTL_MASK)

			return NULL;

		pdata->protctl = tmp;

	}



	return pdata;

}

#else

drivers/dma/dw/regs.h

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@@ -200,6 +200,10 @@ enum dw_dma_msize { 
#define DWC_CFGH_FCMODE		(1 << 0)

#define DWC_CFGH_FIFO_MODE	(1 << 1)

#define DWC_CFGH_PROTCTL(x)	((x) << 2)

#define DWC_CFGH_PROTCTL_DATA	(0 << 2)	/* data access - always set */

#define DWC_CFGH_PROTCTL_PRIV	(1 << 2)	/* privileged -> AHB HPROT[1] */

#define DWC_CFGH_PROTCTL_BUFFER	(2 << 2)	/* bufferable -> AHB HPROT[2] */

#define DWC_CFGH_PROTCTL_CACHE	(4 << 2)	/* cacheable  -> AHB HPROT[3] */

#define DWC_CFGH_DS_UPD_EN	(1 << 5)

#define DWC_CFGH_SS_UPD_EN	(1 << 6)

#define DWC_CFGH_SRC_PER(x)	((x) << 7)