Merge tag 'amd-drm-next-5.19-2022-05-18' of...

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o \

	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o

	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o

amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o

amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \

	nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o

# add DF block

amdgpu-y += \

	gmc_v8_0.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \

	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \

	mmhub_v1_7.o

	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o

# add UMC block

amdgpu-y += \

	cz_ih.o \

	vega10_ih.o \

	vega20_ih.o \

	navi10_ih.o

	navi10_ih.o \

	ih_v6_0.o

# add PSP block

amdgpu-y += \

	gfx_v9_0.o \

	gfx_v9_4.o \

	gfx_v9_4_2.o \

	gfx_v10_0.o

	gfx_v10_0.o \

	imu_v11_0.o \

	gfx_v11_0.o

# add async DMA block

amdgpu-y += \

	sdma_v4_0.o \

	sdma_v4_4.o \

	sdma_v5_0.o \

	sdma_v5_2.o

	sdma_v5_2.o \

	sdma_v6_0.o

# add MES block

amdgpu-y += \

	mes_v10_1.o

	amdgpu_mes.o \

	mes_v10_1.o \

	mes_v11_0.o

# add UVD block

amdgpu-y += \

# add VCN and JPEG block

amdgpu-y += \

	amdgpu_vcn.o \

	vcn_sw_ring.o \

	vcn_v1_0.o \

	vcn_v2_0.o \

	vcn_v2_5.o \

	vcn_v3_0.o \

	vcn_v4_0.o \

	amdgpu_jpeg.o \

	jpeg_v1_0.o \

	jpeg_v2_0.o \

	jpeg_v2_5.o \

	jpeg_v3_0.o

	jpeg_v3_0.o \

	jpeg_v4_0.o

# add ATHUB block

amdgpu-y += \

	athub_v1_0.o \

	athub_v2_0.o \

	athub_v2_1.o

	athub_v2_1.o \

	athub_v3_0.o

# add SMUIO block

amdgpu-y += \

	smuio_v9_0.o \

	smuio_v11_0.o \

	smuio_v11_0_6.o \

	smuio_v13_0.o

	smuio_v13_0.o \

	smuio_v13_0_6.o

# add reset block

amdgpu-y += \

	amdgpu_amdkfd_arcturus.o \

	amdgpu_amdkfd_aldebaran.o \

	amdgpu_amdkfd_gfx_v10.o \

	amdgpu_amdkfd_gfx_v10_3.o

	amdgpu_amdkfd_gfx_v10_3.o \

	amdgpu_amdkfd_gfx_v11.o

ifneq ($(CONFIG_DRM_AMDGPU_CIK),)

amdgpu-y += amdgpu_amdkfd_gfx_v7.o

#include "amdgpu_gmc.h"

#include "amdgpu_gfx.h"

#include "amdgpu_sdma.h"

#include "amdgpu_lsdma.h"

#include "amdgpu_nbio.h"

#include "amdgpu_hdp.h"

#include "amdgpu_dm.h"

#include "amdgpu_virt.h"

#include "amdgpu_csa.h"

#include "amdgpu_mes_ctx.h"

#include "amdgpu_gart.h"

#include "amdgpu_debugfs.h"

#include "amdgpu_job.h"

extern int amdgpu_mcbp;

extern int amdgpu_discovery;

extern int amdgpu_mes;

extern int amdgpu_mes_kiq;

extern int amdgpu_noretry;

extern int amdgpu_force_asic_type;

extern int amdgpu_smartshift_bias;

	SDMA5_HWIP,

	SDMA6_HWIP,

	SDMA7_HWIP,

	LSDMA_HWIP,

	MMHUB_HWIP,

	ATHUB_HWIP,

	NBIO_HWIP,

					  (rid == 0x01) || \

					  (rid == 0x10))))

struct amdgpu_mqd_prop {

	uint64_t mqd_gpu_addr;

	uint64_t hqd_base_gpu_addr;

	uint64_t rptr_gpu_addr;

	uint64_t wptr_gpu_addr;

	uint32_t queue_size;

	bool use_doorbell;

	uint32_t doorbell_index;

	uint64_t eop_gpu_addr;

	uint32_t hqd_pipe_priority;

	uint32_t hqd_queue_priority;

	bool hqd_active;

};

struct amdgpu_mqd {

	unsigned mqd_size;

	int (*init_mqd)(struct amdgpu_device *adev, void *mqd,

			struct amdgpu_mqd_prop *p);

};

#define AMDGPU_RESET_MAGIC_NUM 64

#define AMDGPU_MAX_DF_PERFMONS 4

#define AMDGPU_PRODUCT_NAME_LEN 64

	/* sdma */

	struct amdgpu_sdma		sdma;

	/* lsdma */

	struct amdgpu_lsdma		lsdma;

	/* uvd */

	struct amdgpu_uvd		uvd;

	/* mes */

	bool                            enable_mes;

	bool                            enable_mes_kiq;

	struct amdgpu_mes               mes;

	struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];

	/* df */

	struct amdgpu_df                df;

	bool                            runpm;

	bool                            in_runpm;

	bool                            has_pr3;

	bool                            is_fw_fb;

	bool                            pm_sysfs_en;

	bool                            ucode_sysfs_en;

	bool                            psp_sysfs_en;

	/* Chip product information */

	char				product_number[16];

	/* reset dump register */

	uint32_t                        *reset_dump_reg_list;

	int                             num_regs;

	bool                            scpm_enabled;

	uint32_t                        scpm_status;

};

static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

#define amdgpu_asic_flush_hdp(adev, r) \

	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))

#define amdgpu_asic_invalidate_hdp(adev, r) \

	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))

	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \

	 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))

#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))

#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))

#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))

#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)

bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);

bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);

bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);

#else

static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }

static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }

static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }

#endif

		(pm_suspend_target_state == PM_SUSPEND_MEM);

}

/**

 * amdgpu_acpi_should_gpu_reset

 *

 * @adev: amdgpu_device_pointer

 *

 * returns true if should reset GPU, false if not

 */

bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)

{

	if (adev->flags & AMD_IS_APU)

		return false;

	return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;

}

/**

 * amdgpu_acpi_is_s0ix_active

 *

	 * The first num_doorbells are used by amdgpu.

	 * amdkfd takes whatever's left in the aperture.

	 */

	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {

	if (adev->enable_mes) {

		/*

		 * With MES enabled, we only need to initialize

		 * the base address. The size and offset are

		 * not initialized as AMDGPU manages the whole

		 * doorbell space.

		 */

		*aperture_base = adev->doorbell.base;

		*aperture_size = 0;

		*start_offset = 0;

	} else if (adev->doorbell.size > adev->doorbell.num_doorbells *

						sizeof(u32)) {

		*aperture_base = adev->doorbell.base;

		*aperture_size = adev->doorbell.size;

		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);

					  AMDGPU_GMC_HOLE_START),

			.drm_render_minor = adev_to_drm(adev)->render->index,

			.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,

			.enable_mes = adev->enable_mes,

		};

		/* this is going to have a few of the MSBs set that we need to