Commit 00d1f9c6 authored by Valentin Caron's avatar Valentin Caron Committed by Greg Kroah-Hartman
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serial: stm32: modify parameter and rename stm32_usart_rx_dma_enabled 



Rename stm32_usart_rx_dma_enabled to stm32_usart_rx_dma_started in order
to match with stm32_usart_tx_dma_started.

Modify argument of stm32_usart_rx_dma_started from uart_port structure to
stm32_port structure to match with stm32_usart_tx_dma_started.

Signed-off-by: default avatarValentin Caron <valentin.caron@foss.st.com>
Link: https://lore.kernel.org/r/20230808161906.178996-4-valentin.caron@foss.st.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 00bc5e8f

drivers/tty/serial/stm32-usart.c

+8 −8
Original line number Diff line number Diff line
@@ -289,9 +289,9 @@ static int stm32_usart_init_rs485(struct uart_port *port, 
	return uart_get_rs485_mode(port);

}



static bool stm32_usart_rx_dma_enabled(struct uart_port *port)

static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port)

{

	struct stm32_port *stm32_port = to_stm32_port(port);

	struct uart_port *port = &stm32_port->port;

	const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;



	if (!stm32_port->rx_ch)
@@ -310,7 +310,7 @@ static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr) 
	/* Get pending characters in RDR or FIFO */

	if (*sr & USART_SR_RXNE) {

		/* Get all pending characters from the RDR or the FIFO when using interrupts */

		if (!stm32_usart_rx_dma_enabled(port))

		if (!stm32_usart_rx_dma_started(stm32_port))

			return true;



		/* Handle only RX data errors when using DMA */
@@ -455,7 +455,7 @@ static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force 
	u32 sr;

	unsigned int size = 0;



	if (stm32_usart_rx_dma_enabled(port) || force_dma_flush) {

	if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) {

		rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,

						    stm32_port->rx_ch->cookie,

						    &stm32_port->rx_dma_state);
@@ -789,8 +789,8 @@ static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 
	 * line has been masked by HW and rx data are stacking in FIFO.

	 */

	if (!stm32_port->throttled) {

		if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_enabled(port)) ||

		    ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_enabled(port))) {

		if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||

		    ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {

			spin_lock(&port->lock);

			size = stm32_usart_receive_chars(port, false);

			uart_unlock_and_check_sysrq(port);
@@ -806,7 +806,7 @@ static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 
	}



	/* Receiver timeout irq for DMA RX */

	if (stm32_usart_rx_dma_enabled(port) && !stm32_port->throttled) {

	if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {

		spin_lock(&port->lock);

		size = stm32_usart_receive_chars(port, false);

		uart_unlock_and_check_sysrq(port);
@@ -906,7 +906,7 @@ static void stm32_usart_throttle(struct uart_port *port) 
	 * Disable DMA request line if enabled, so the RX data gets queued into the FIFO.

	 * Hardware flow control is triggered when RX FIFO is full.

	 */

	if (stm32_usart_rx_dma_enabled(port))

	if (stm32_usart_rx_dma_started(stm32_port))

		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);



	stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);