Commit 00c6cbfd authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move pipe_mask and cpu_transcoder_mask to runtime info 



If it's modified runtime, it's runtime info.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMaarten Lankhort <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bff2ea209031063cec38085518508394b064df4a.1660910433.git.jani.nikula@intel.com
parent 488e29fe

drivers/gpu/drm/i915/display/intel_display.h

+2 −2
Original line number Diff line number Diff line
@@ -375,7 +375,7 @@ enum hpd_pin { 


#define for_each_pipe(__dev_priv, __p) \

	for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \

		for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))

		for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))



#define for_each_pipe_masked(__dev_priv, __p, __mask) \

	for_each_pipe(__dev_priv, __p) \
@@ -383,7 +383,7 @@ enum hpd_pin { 


#define for_each_cpu_transcoder(__dev_priv, __t) \

	for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)	\

		for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))

		for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))



#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \

	for_each_cpu_transcoder(__dev_priv, __t) \

drivers/gpu/drm/i915/i915_drv.h

+3 −3
Original line number Diff line number Diff line
@@ -1264,7 +1264,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define HAS_PSR_HW_TRACKING(dev_priv) \

	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)

#define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)

#define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)

#define HAS_TRANSCODER(dev_priv, trans)	 ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)



#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)

#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
@@ -1335,9 +1335,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define GT_FREQUENCY_MULTIPLIER 50

#define GEN9_FREQ_SCALER 3



#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))

#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))



#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)

#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)



#define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)

drivers/gpu/drm/i915/i915_pci.c

+33 −33
Original line number Diff line number Diff line
@@ -168,8 +168,8 @@ 
#define I830_FEATURES \

	GEN(2), \

	.is_mobile = 1, \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_overlay = 1, \

	.display.cursor_needs_physical = 1, \

	.display.overlay_needs_physical = 1, \
@@ -190,8 +190,8 @@ 


#define I845_FEATURES \

	GEN(2), \

	.display.pipe_mask = BIT(PIPE_A), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A), \

	.__runtime.pipe_mask = BIT(PIPE_A), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \

	.display.has_overlay = 1, \

	.display.overlay_needs_physical = 1, \

	.display.has_gmch = 1, \
@@ -233,8 +233,8 @@ static const struct intel_device_info i865g_info = { 


#define GEN3_FEATURES \

	GEN(3), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_gmch = 1, \

	.gpu_reset_clobbers_display = true, \

	.__runtime.platform_engine_mask = BIT(RCS0), \
@@ -324,8 +324,8 @@ static const struct intel_device_info pnv_m_info = { 


#define GEN4_FEATURES \

	GEN(4), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_hotplug = 1, \

	.display.has_gmch = 1, \

	.gpu_reset_clobbers_display = true, \
@@ -378,8 +378,8 @@ static const struct intel_device_info gm45_info = { 


#define GEN5_FEATURES \

	GEN(5), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_hotplug = 1, \

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \

	.has_3d_pipeline = 1, \
@@ -409,8 +409,8 @@ static const struct intel_device_info ilk_m_info = { 


#define GEN6_FEATURES \

	GEN(6), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_hotplug = 1, \

	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -461,8 +461,8 @@ static const struct intel_device_info snb_m_gt2_info = { 


#define GEN7_FEATURES  \

	GEN(7), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \

	.display.has_hotplug = 1, \

	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -517,8 +517,8 @@ static const struct intel_device_info ivb_q_info = { 
	GEN7_FEATURES,

	PLATFORM(INTEL_IVYBRIDGE),

	.gt = 2,

	.display.pipe_mask = 0, /* legal, last one wins */

	.display.cpu_transcoder_mask = 0,

	.__runtime.pipe_mask = 0, /* legal, last one wins */

	.__runtime.cpu_transcoder_mask = 0,

	.has_l3_dpf = 1,

};
@@ -526,8 +526,8 @@ static const struct intel_device_info vlv_info = { 
	PLATFORM(INTEL_VALLEYVIEW),

	GEN(7),

	.is_lp = 1,

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),

	.has_runtime_pm = 1,

	.has_rc6 = 1,

	.has_reset_engine = true,
@@ -551,7 +551,7 @@ static const struct intel_device_info vlv_info = { 
#define G75_FEATURES  \

	GEN7_FEATURES, \

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \

	.display.has_ddi = 1, \

	.display.has_fpga_dbg = 1, \
@@ -621,8 +621,8 @@ static const struct intel_device_info bdw_gt3_info = { 
static const struct intel_device_info chv_info = {

	PLATFORM(INTEL_CHERRYVIEW),

	GEN(8),

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),

	.display.has_hotplug = 1,

	.is_lp = 1,

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -699,8 +699,8 @@ static const struct intel_device_info skl_gt4_info = { 
	.display.dbuf.slice_mask = BIT(DBUF_S1), \

	.display.has_hotplug = 1, \

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \

		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \

	.has_3d_pipeline = 1, \
@@ -810,7 +810,7 @@ static const struct intel_device_info cml_gt2_info = { 
	GEN9_FEATURES, \

	GEN11_DEFAULT_PAGE_SIZES, \

	.display.abox_mask = BIT(0), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \

		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \

	.display.pipe_offsets = { \
@@ -862,8 +862,8 @@ static const struct intel_device_info jsl_info = { 
	GEN11_FEATURES, \

	GEN(12), \

	.display.abox_mask = GENMASK(2, 1), \

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \

		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \

		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \

	.display.pipe_offsets = { \
@@ -899,8 +899,8 @@ static const struct intel_device_info rkl_info = { 
	GEN12_FEATURES,

	PLATFORM(INTEL_ROCKETLAKE),

	.display.abox_mask = BIT(0),

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

		BIT(TRANSCODER_C),

	.display.has_hti = 1,

	.display.has_psr_hw_tracking = 0,
@@ -921,7 +921,7 @@ static const struct intel_device_info dg1_info = { 
	DGFX_FEATURES,

	.__runtime.graphics.rel = 10,

	PLATFORM(INTEL_DG1),

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

	.require_force_probe = 1,

	.__runtime.platform_engine_mask =

		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -933,7 +933,7 @@ static const struct intel_device_info dg1_info = { 
static const struct intel_device_info adl_s_info = {

	GEN12_FEATURES,

	PLATFORM(INTEL_ALDERLAKE_S),

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

	.display.has_hti = 1,

	.display.has_psr_hw_tracking = 0,

	.__runtime.platform_engine_mask =
@@ -963,7 +963,7 @@ static const struct intel_device_info adl_s_info = { 
	.display.has_ipc = 1,							\

	.display.has_psr = 1,							\

	.display.ver = 13,							\

	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\

	.__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),	\

	.display.pipe_offsets = {						\

		[TRANSCODER_A] = PIPE_A_OFFSET,					\

		[TRANSCODER_B] = PIPE_B_OFFSET,					\
@@ -986,7 +986,7 @@ static const struct intel_device_info adl_p_info = { 
	GEN12_FEATURES,

	XE_LPD_FEATURES,

	PLATFORM(INTEL_ALDERLAKE_P),

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |

			       BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),

	.display.has_cdclk_crawl = 1,
@@ -1071,7 +1071,7 @@ static const struct intel_device_info xehpsdv_info = { 
static const struct intel_device_info dg2_info = {

	DG2_FEATURES,

	XE_LPD_FEATURES,

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

	.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),

	.require_force_probe = 1,

};

drivers/gpu/drm/i915/intel_device_info.c

+12 −12
Original line number Diff line number Diff line
@@ -363,35 +363,35 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {

			drm_info(&dev_priv->drm,

				 "Display fused off, disabling\n");

			info->display.pipe_mask = 0;

			info->display.cpu_transcoder_mask = 0;

			runtime->pipe_mask = 0;

			runtime->cpu_transcoder_mask = 0;

			runtime->fbc_mask = 0;

		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {

			drm_info(&dev_priv->drm, "PipeC fused off\n");

			info->display.pipe_mask &= ~BIT(PIPE_C);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

			runtime->pipe_mask &= ~BIT(PIPE_C);

			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

		}

	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {

		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);



		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {

			info->display.pipe_mask &= ~BIT(PIPE_A);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);

			runtime->pipe_mask &= ~BIT(PIPE_A);

			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);

			runtime->fbc_mask &= ~BIT(INTEL_FBC_A);

		}

		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {

			info->display.pipe_mask &= ~BIT(PIPE_B);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);

			runtime->pipe_mask &= ~BIT(PIPE_B);

			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);

		}

		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {

			info->display.pipe_mask &= ~BIT(PIPE_C);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

			runtime->pipe_mask &= ~BIT(PIPE_C);

			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

		}



		if (DISPLAY_VER(dev_priv) >= 12 &&

		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {

			info->display.pipe_mask &= ~BIT(PIPE_D);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);

			runtime->pipe_mask &= ~BIT(PIPE_D);

			runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);

		}



		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)

drivers/gpu/drm/i915/intel_device_info.h

+3 −2
Original line number Diff line number Diff line
@@ -233,6 +233,9 @@ struct intel_runtime_info { 


	/* display */

	struct {

		u8 pipe_mask;

		u8 cpu_transcoder_mask;



		u8 num_sprites[I915_MAX_PIPES];

		u8 num_scalers[I915_MAX_PIPES];
@@ -257,8 +260,6 @@ struct intel_device_info { 
		u8 ver;

		u8 rel;



		u8 pipe_mask;

		u8 cpu_transcoder_mask;

		u8 abox_mask;



		struct {