Commit 00a9f717 authored by Amelie Delaunay's avatar Amelie Delaunay Committed by Vinod Koul
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dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node



PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE
signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
parent node and not in phy children nodes.

Signed-off-by: default avatarAmelie Delaunay <amelie.delaunay@foss.st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210105090525.23164-2-amelie.delaunay@foss.st.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 34168172
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+10 −12
Original line number Diff line number Diff line
@@ -45,6 +45,12 @@ properties:
  "#size-cells":
    const: 0

  vdda1v1-supply:
    description: regulator providing 1V1 power supply to the PLL block

  vdda1v8-supply:
    description: regulator providing 1V8 power supply to the PLL block

#Required child nodes:

patternProperties:
@@ -61,12 +67,6 @@ patternProperties:
      phy-supply:
        description: regulator providing 3V3 power supply to the PHY.

      vdda1v1-supply:
        description: regulator providing 1V1 power supply to the PLL block

      vdda1v8-supply:
        description: regulator providing 1V8 power supply to the PLL block

      "#phy-cells":
        enum: [ 0x0, 0x1 ]

@@ -90,8 +90,6 @@ patternProperties:
    required:
      - reg
      - phy-supply
      - vdda1v1-supply
      - vdda1v8-supply
      - "#phy-cells"

    additionalProperties: false
@@ -102,6 +100,8 @@ required:
  - clocks
  - "#address-cells"
  - "#size-cells"
  - vdda1v1-supply
  - vdda1v8-supply
  - usb-phy@0
  - usb-phy@1

@@ -116,22 +116,20 @@ examples:
        reg = <0x5a006000 0x1000>;
        clocks = <&rcc USBPHY_K>;
        resets = <&rcc USBPHY_R>;
        vdda1v1-supply = <&reg11>;
        vdda1v8-supply = <&reg18>;
        #address-cells = <1>;
        #size-cells = <0>;

        usbphyc_port0: usb-phy@0 {
            reg = <0>;
            phy-supply = <&vdd_usb>;
            vdda1v1-supply = <&reg11>;
            vdda1v8-supply = <&reg18>;
            #phy-cells = <0>;
        };

        usbphyc_port1: usb-phy@1 {
            reg = <1>;
            phy-supply = <&vdd_usb>;
            vdda1v1-supply = <&reg11>;
            vdda1v8-supply = <&reg18>;
            #phy-cells = <1>;
        };
    };