Commit 00a2f23e authored by Tony Luck's avatar Tony Luck Committed by Borislav Petkov
Browse files

x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit 



After nine generations of adding to model specific list of CPUs that
support PPIN (Protected Processor Inventory Number) Intel allocated
a CPUID bit to enumerate the MSRs.

CPUID(EAX=7, ECX=1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and
MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the
ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement
it.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220131230111.2004669-3-tony.luck@intel.com
parent 0dcab41d

arch/x86/kernel/cpu/common.c

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ static struct ppin_info { 


static const struct x86_cpu_id ppin_cpuids[] = {

	X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),

	X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),



	/* Legacy models without CPUID enumeration */

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ struct cpuid_bit { 
static const struct cpuid_bit cpuid_bits[] = {

	{ X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },

	{ X86_FEATURE_EPB,		CPUID_ECX,  3, 0x00000006, 0 },

	{ X86_FEATURE_INTEL_PPIN,	CPUID_EBX,  0, 0x00000007, 1 },

	{ X86_FEATURE_CQM_LLC,		CPUID_EDX,  1, 0x0000000f, 0 },

	{ X86_FEATURE_CQM_OCCUP_LLC,	CPUID_EDX,  0, 0x0000000f, 1 },

	{ X86_FEATURE_CQM_MBM_TOTAL,	CPUID_EDX,  1, 0x0000000f, 1 },