+17
−0
+188
−1
+199
−1
drivers/staging/wfx/hwio.h
0 → 100644
+48
−0
+53
−0
Loading
Introduce bus level communication layer. At this level, 7 registers can be addressed. Notice that SPI driver is able to manage chip reset. SDIO mode relies on an external driver (`mmc-pwrseq`) to reset chip. Signed-off-by:Jérôme Pouiller <jerome.pouiller@silabs.com> Link: https://lore.kernel.org/r/20190919142527.31797-3-Jerome.Pouiller@silabs.com Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>