drm/msm/dsi: drop msm_dsi_pll abstraction (007687c3) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/msm/Kconfig

+0 −8

Original line number	Diff line number	Diff line
		@@ -77,14 +77,6 @@ config DRM_MSM_DSI
		Choose this option if you have a need for MIPI DSI connector
		support.

		config DRM_MSM_DSI_PLL
		bool "Enable DSI PLL driver in MSM DRM"
		depends on DRM_MSM_DSI && COMMON_CLK
		default y
		help
		Choose this option to enable DSI PLL driver which provides DSI
		source clocks under common clock framework.

		config DRM_MSM_DSI_28NM_PHY
		bool "Enable DSI 28nm PHY driver in MSM DRM"
		depends on DRM_MSM_DSI

drivers/gpu/drm/msm/Makefile

+0 −2

Original line number	Diff line number	Diff line
		@@ -136,6 +136,4 @@ msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
		msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
		msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o

		msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/phy/dsi_pll.o

		obj-$(CONFIG_DRM_MSM) += msm.o

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+25 −11

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@
		#define __DSI_PHY_H__

		#include <linux/clk-provider.h>
		#include <linux/delay.h>
		#include <linux/regulator/consumer.h>

		#include "dsi.h"
		@@ -14,15 +15,6 @@
		#define dsi_phy_read(offset) msm_readl((offset))
		#define dsi_phy_write(offset, data) msm_writel((data), (offset))

		struct msm_dsi_pll {
		struct clk_hw clk_hw;
		bool pll_on;

		const struct msm_dsi_phy_cfg *cfg;
		};

		#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)

		struct msm_dsi_phy_ops {
		int (pll_init)(struct msm_dsi_phy phy);
		int (enable)(struct msm_dsi_phy phy, int src_pll_id,
		@@ -107,7 +99,8 @@ struct msm_dsi_phy {
		enum msm_dsi_phy_usecase usecase;
		bool regulator_ldo_mode;

		struct msm_dsi_pll *pll;
		struct clk_hw *vco_hw;
		bool pll_on;

		struct clk_hw_onecell_data *provided_clocks;

		@@ -127,6 +120,27 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
		struct msm_dsi_phy_clk_request *clk_req);
		void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
		u32 bit_mask);
		/* PLL accessors */
		static inline void pll_write(void __iomem *reg, u32 data)
		{
		msm_writel(data, reg);
		}

		static inline u32 pll_read(const void __iomem *reg)
		{
		return msm_readl(reg);
		}

		static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
		{
		pll_write(reg, data);
		udelay(delay_us);
		}

		static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
		{
		pll_write((reg), data);
		ndelay(delay_ns);
		}

		#endif /* __DSI_PHY_H__ */

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+35 −31

Original line number	Diff line number	Diff line
		@@ -7,7 +7,6 @@
		#include <linux/clk-provider.h>
		#include <linux/iopoll.h>

		#include "dsi_pll.h"
		#include "dsi_phy.h"
		#include "dsi.xml.h"

		@@ -85,11 +84,13 @@ struct pll_10nm_cached_state {
		};

		struct dsi_pll_10nm {
		struct msm_dsi_pll base;
		struct clk_hw clk_hw;

		int id;
		struct platform_device *pdev;

		struct msm_dsi_phy *phy;

		void __iomem *phy_cmn_mmio;
		void __iomem *mmio;

		@@ -104,11 +105,10 @@ struct dsi_pll_10nm {

		struct pll_10nm_cached_state cached_state;

		enum msm_dsi_phy_usecase uc;
		struct dsi_pll_10nm *slave;
		};

		#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base)
		#define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw)

		/*
		* Global list of private DSI PLL struct pointers. We need this for Dual DSI
		@@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll)
		static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);

		DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
		parent_rate);
		@@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)

		static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
		struct device *dev = &pll_10nm->pdev->dev;
		int rc;

		@@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
		goto error;
		}

		pll->pll_on = true;
		pll_10nm->phy->pll_on = true;

		dsi_pll_enable_global_clk(pll_10nm);
		if (pll_10nm->slave)
		@@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)

		static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);

		/*
		* To avoid any stray glitches while abruptly powering down the PLL
		@@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
		}
		/* flush, ensure all register writes are done */
		wmb();
		pll->pll_on = false;
		pll_10nm->phy->pll_on = false;
		}

		static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
		struct dsi_pll_config *config = &pll_10nm->pll_configuration;
		void __iomem *base = pll_10nm->mmio;
		u64 ref_clk = pll_10nm->vco_ref_clk_rate;
		@@ -506,8 +502,21 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
		return (unsigned long)vco_rate;
		}

		static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *parent_rate)
		{
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);

		if (rate < pll_10nm->phy->cfg->min_pll_rate)
		return pll_10nm->phy->cfg->min_pll_rate;
		else if (rate > pll_10nm->phy->cfg->max_pll_rate)
		return pll_10nm->phy->cfg->max_pll_rate;
		else
		return rate;
		}

		static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
		.round_rate = msm_dsi_pll_helper_clk_round_rate,
		.round_rate = dsi_pll_10nm_clk_round_rate,
		.set_rate = dsi_pll_10nm_vco_set_rate,
		.recalc_rate = dsi_pll_10nm_vco_recalc_rate,
		.prepare = dsi_pll_10nm_vco_prepare,
		@@ -520,7 +529,7 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {

		static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
		struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
		void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
		u32 cmn_clk_cfg0, cmn_clk_cfg1;
		@@ -543,7 +552,7 @@ static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)

		static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
		struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
		void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
		u32 val;
		@@ -562,7 +571,7 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
		val \|= cached->pll_mux;
		pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);

		ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw,
		ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
		pll_10nm->vco_current_rate,
		pll_10nm->vco_ref_clk_rate);
		if (ret) {
		@@ -576,16 +585,15 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
		return 0;
		}

		static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
		enum msm_dsi_phy_usecase uc)
		static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
		struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
		void __iomem *base = pll_10nm->phy_cmn_mmio;
		u32 data = 0x0; /* internal PLL */

		DBG("DSI PLL%d", pll_10nm->id);

		switch (uc) {
		switch (phy->usecase) {
		case MSM_DSI_PHY_STANDALONE:
		break;
		case MSM_DSI_PHY_MASTER:
		@@ -601,8 +609,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
		/* set PLL src */
		pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));

		pll_10nm->uc = uc;

		return 0;
		}

		@@ -630,9 +636,9 @@ static int pll_10nm_register(struct dsi_pll_10nm pll_10nm, struct clk_hw *prov
		DBG("DSI%d", pll_10nm->id);

		snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
		pll_10nm->base.clk_hw.init = &vco_init;
		pll_10nm->clk_hw.init = &vco_init;

		ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
		ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
		if (ret)
		return ret;

		@@ -742,7 +748,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
		struct platform_device *pdev = phy->pdev;
		int id = phy->id;
		struct dsi_pll_10nm *pll_10nm;
		struct msm_dsi_pll *pll;
		int ret;

		pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
		@@ -769,8 +774,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)

		spin_lock_init(&pll_10nm->postdiv_lock);

		pll = &pll_10nm->base;
		pll->cfg = phy->cfg;
		pll_10nm->phy = phy;

		ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
		if (ret) {
		@@ -778,7 +782,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
		return ret;
		}

		phy->pll = pll;
		phy->vco_hw = &pll_10nm->clk_hw;

		/* TODO: Remove this when we have proper display handover support */
		msm_dsi_phy_pll_save_state(phy);
		@@ -953,7 +957,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
		/* Select full-rate mode */
		dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);

		ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
		ret = dsi_10nm_set_usecase(phy);
		if (ret) {
		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
		__func__, ret);

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+41 −37

Original line number	Diff line number	Diff line
		@@ -8,7 +8,6 @@
		#include <linux/delay.h>

		#include "dsi_phy.h"
		#include "dsi_pll.h"
		#include "dsi.xml.h"

		#define PHY_14NM_CKLN_IDX 4
		@@ -114,7 +113,7 @@ struct pll_14nm_cached_state {
		};

		struct dsi_pll_14nm {
		struct msm_dsi_pll base;
		struct clk_hw clk_hw;

		int id;
		struct platform_device *pdev;
		@@ -122,6 +121,8 @@ struct dsi_pll_14nm {
		void __iomem *phy_cmn_mmio;
		void __iomem *mmio;

		struct msm_dsi_phy *phy;

		struct dsi_pll_input in;
		struct dsi_pll_output out;

		@@ -133,11 +134,10 @@ struct dsi_pll_14nm {

		struct pll_14nm_cached_state cached_state;

		enum msm_dsi_phy_usecase uc;
		struct dsi_pll_14nm *slave;
		};

		#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
		#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw)

		/*
		* Private struct for N1/N2 post-divider clocks. These clocks are similar to
		@@ -564,8 +564,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
		static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
		struct dsi_pll_input *pin = &pll_14nm->in;
		struct dsi_pll_output *pout = &pll_14nm->out;

		@@ -600,7 +599,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
		* don't lock the slave PLL. We just ensure that the PLL/PHY registers
		* of the master and slave are identical
		*/
		if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
		if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;

		pll_db_commit_14nm(pll_14nm_slave, pin, pout);
		@@ -614,8 +613,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
		static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
		void __iomem *base = pll_14nm->mmio;
		u64 vco_rate, multiplier = BIT(20);
		u32 div_frac_start;
		@@ -654,15 +652,14 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,

		static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
		void __iomem *base = pll_14nm->mmio;
		void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
		bool locked;

		DBG("");

		if (unlikely(pll->pll_on))
		if (unlikely(pll_14nm->phy->pll_on))
		return 0;

		pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
		@@ -677,29 +674,41 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
		}

		DBG("DSI PLL lock success");
		pll->pll_on = true;
		pll_14nm->phy->pll_on = true;

		return 0;
		}

		static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
		{
		struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
		void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;

		DBG("");

		if (unlikely(!pll->pll_on))
		if (unlikely(!pll_14nm->phy->pll_on))
		return;

		pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);

		pll->pll_on = false;
		pll_14nm->phy->pll_on = false;
		}

		static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
		unsigned long rate, unsigned long *parent_rate)
		{
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);

		if (rate < pll_14nm->phy->cfg->min_pll_rate)
		return pll_14nm->phy->cfg->min_pll_rate;
		else if (rate > pll_14nm->phy->cfg->max_pll_rate)
		return pll_14nm->phy->cfg->max_pll_rate;
		else
		return rate;
		}

		static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
		.round_rate = msm_dsi_pll_helper_clk_round_rate,
		.round_rate = dsi_pll_14nm_clk_round_rate,
		.set_rate = dsi_pll_14nm_vco_set_rate,
		.recalc_rate = dsi_pll_14nm_vco_recalc_rate,
		.prepare = dsi_pll_14nm_vco_prepare,
		@@ -773,7 +782,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
		/* If we're master in dual DSI mode, then the slave PLL's post-dividers
		* follow the master's post dividers
		*/
		if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
		if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
		void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;

		@@ -797,7 +806,7 @@ static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {

		static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
		struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
		void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
		u32 data;
		@@ -810,18 +819,18 @@ static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
		DBG("DSI%d PLL save state %x %x", pll_14nm->id,
		cached_state->n1postdiv, cached_state->n2postdiv);

		cached_state->vco_rate = clk_hw_get_rate(&phy->pll->clk_hw);
		cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
		}

		static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
		struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
		void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
		u32 data;
		int ret;

		ret = dsi_pll_14nm_vco_set_rate(&phy->pll->clk_hw,
		ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
		cached_state->vco_rate, 0);
		if (ret) {
		DRM_DEV_ERROR(&pll_14nm->pdev->dev,
		@@ -837,7 +846,7 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
		pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);

		/* also restore post-dividers for slave DSI PLL */
		if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
		if (phy->usecase == MSM_DSI_PHY_MASTER) {
		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
		void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;

		@@ -847,14 +856,13 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
		return 0;
		}

		static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
		enum msm_dsi_phy_usecase uc)
		static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
		{
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
		struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
		void __iomem *base = pll_14nm->mmio;
		u32 clkbuflr_en, bandgap = 0;

		switch (uc) {
		switch (phy->usecase) {
		case MSM_DSI_PHY_STANDALONE:
		clkbuflr_en = 0x1;
		break;
		@@ -874,8 +882,6 @@ static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
		if (bandgap)
		pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);

		pll_14nm->uc = uc;

		return 0;
		}

		@@ -932,9 +938,9 @@ static int pll_14nm_register(struct dsi_pll_14nm pll_14nm, struct clk_hw *prov
		DBG("DSI%d", pll_14nm->id);

		snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
		pll_14nm->base.clk_hw.init = &vco_init;
		pll_14nm->clk_hw.init = &vco_init;

		ret = devm_clk_hw_register(dev, &pll_14nm->base.clk_hw);
		ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
		if (ret)
		return ret;

		@@ -990,7 +996,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
		struct platform_device *pdev = phy->pdev;
		int id = phy->id;
		struct dsi_pll_14nm *pll_14nm;
		struct msm_dsi_pll *pll;
		int ret;

		if (!pdev)
		@@ -1020,8 +1025,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)

		spin_lock_init(&pll_14nm->postdiv_lock);

		pll = &pll_14nm->base;
		pll->cfg = phy->cfg;
		pll_14nm->phy = phy;

		ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
		if (ret) {
		@@ -1029,7 +1033,7 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
		return ret;
		}

		phy->pll = pll;
		phy->vco_hw = &pll_14nm->clk_hw;

		return 0;
		}
		@@ -1131,7 +1135,7 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
		REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
		DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);

		ret = dsi_pll_14nm_set_usecase(phy->pll, phy->usecase);
		ret = dsi_14nm_set_usecase(phy);
		if (ret) {
		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
		__func__, ret);