Commit 005e9537 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/display: Eliminate most usage of INTEL_GEN() 



Use Coccinelle to convert most of the usage of INTEL_GEN() and IS_GEN()
in the display code to use DISPLAY_VER() comparisons instead.  The
following semantic patch was used:

        @@ expression dev_priv, E; @@
        - INTEL_GEN(dev_priv) == E
        + IS_DISPLAY_VER(dev_priv, E)

        @@ expression dev_priv; @@
        - INTEL_GEN(dev_priv)
        + DISPLAY_VER(dev_priv)

        @@ expression dev_priv; expression E; @@
        - IS_GEN(dev_priv, E)
        + IS_DISPLAY_VER(dev_priv, E)

        @@
        expression dev_priv;
        expression from, until;
        @@
        - IS_GEN_RANGE(dev_priv, from, until)
        + IS_DISPLAY_RANGE(dev_priv, from, until)

There are still some display-related uses of INTEL_GEN() in intel_pm.c
(watermark code) and i915_irq.c.  Those will be updated separately.

v2:
 - Use new IS_DISPLAY_RANGE and IS_DISPLAY_VER helpers.  (Jani)

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-4-matthew.d.roper@intel.com
parent 01eb15c9

drivers/gpu/drm/i915/display/i9xx_plane.c

+26 −26
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 
	else if (IS_IVYBRIDGE(dev_priv))

		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||

			i9xx_plane == PLANE_C;

	else if (INTEL_GEN(dev_priv) >= 4)

	else if (DISPLAY_VER(dev_priv) >= 4)

		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;

	else

		return i9xx_plane == PLANE_A;
@@ -141,9 +141,9 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) 


	if (IS_CHERRYVIEW(dev_priv))

		return i9xx_plane == PLANE_B;

	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))

	else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))

		return false;

	else if (IS_GEN(dev_priv, 4))

	else if (IS_DISPLAY_VER(dev_priv, 4))

		return i9xx_plane == PLANE_C;

	else

		return i9xx_plane == PLANE_B ||
@@ -210,7 +210,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 
		return 0;

	}



	if (INTEL_GEN(dev_priv) >= 4 &&

	if (DISPLAY_VER(dev_priv) >= 4 &&

	    fb->modifier == I915_FORMAT_MOD_X_TILED)

		dspcntr |= DISPPLANE_TILED;
@@ -249,7 +249,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 


	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);



	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		offset = intel_plane_compute_aligned_offset(&src_x, &src_y,

							    plane_state, 0);

	else
@@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 
	 * Linear surfaces seem to work just fine, even on hsw/bdw

	 * despite them not using the linear offset anymore.

	 */

	if (INTEL_GEN(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {

	if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {

		u32 alignment = intel_surf_alignment(fb, 0);

		int cpp = fb->format->cpp[0];
@@ -305,7 +305,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 


	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);

	} else if (INTEL_GEN(dev_priv) >= 4 &&

	} else if (DISPLAY_VER(dev_priv) >= 4 &&

		   fb->modifier == I915_FORMAT_MOD_X_TILED) {

		drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);

	}
@@ -363,7 +363,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 
	if (crtc_state->csc_enable)

		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;



	if (INTEL_GEN(dev_priv) < 5)

	if (DISPLAY_VER(dev_priv) < 5)

		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);



	return dspcntr;
@@ -437,7 +437,7 @@ static void i9xx_update_plane(struct intel_plane *plane, 


	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);



	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		dspaddr_offset = plane_state->color_plane[0].offset;

	else

		dspaddr_offset = linear_offset;
@@ -447,7 +447,7 @@ static void i9xx_update_plane(struct intel_plane *plane, 
	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),

			  plane_state->color_plane[0].stride);



	if (INTEL_GEN(dev_priv) < 4) {

	if (DISPLAY_VER(dev_priv) < 4) {

		/*

		 * PLANE_A doesn't actually have a full window

		 * generator but let's assume we still need to
@@ -468,7 +468,7 @@ static void i9xx_update_plane(struct intel_plane *plane, 
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),

				  (y << 16) | x);

	} else if (INTEL_GEN(dev_priv) >= 4) {

	} else if (DISPLAY_VER(dev_priv) >= 4) {

		intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),

				  linear_offset);

		intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
@@ -481,7 +481,7 @@ static void i9xx_update_plane(struct intel_plane *plane, 
	 * the control register just before the surface register.

	 */

	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);

	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),

				  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

	else
@@ -514,7 +514,7 @@ static void i9xx_disable_plane(struct intel_plane *plane, 
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);

	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);

	else

		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
@@ -669,7 +669,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 


	ret = val & DISPLAY_PLANE_ENABLE;



	if (INTEL_GEN(dev_priv) >= 5)

	if (DISPLAY_VER(dev_priv) >= 5)

		*pipe = plane->pipe;

	else

		*pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -729,7 +729,7 @@ i9xx_plane_max_stride(struct intel_plane *plane, 
{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);



	if (INTEL_GEN(dev_priv) >= 3) {

	if (DISPLAY_VER(dev_priv) >= 3) {

		if (modifier == I915_FORMAT_MOD_X_TILED)

			return 8*1024;

		else
@@ -779,7 +779,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS

	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.

	 */

	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&

	if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 &&

	    INTEL_NUM_PIPES(dev_priv) == 2)

		plane->i9xx_plane = (enum i9xx_plane_id) !pipe;

	else
@@ -797,7 +797,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		formats = vlv_primary_formats;

		num_formats = ARRAY_SIZE(vlv_primary_formats);

	} else if (INTEL_GEN(dev_priv) >= 4) {

	} else if (DISPLAY_VER(dev_priv) >= 4) {

		/*

		 * WaFP16GammaEnabling:ivb

		 * "Workaround : When using the 64-bit format, the plane
@@ -823,7 +823,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
		num_formats = ARRAY_SIZE(i8xx_primary_formats);

	}



	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		plane_funcs = &i965_plane_funcs;

	else

		plane_funcs = &i8xx_plane_funcs;
@@ -838,7 +838,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
		plane->min_cdclk = i9xx_plane_min_cdclk;



	if (HAS_GMCH(dev_priv)) {

		if (INTEL_GEN(dev_priv) >= 4)

		if (DISPLAY_VER(dev_priv) >= 4)

			plane->max_stride = i965_plane_max_stride;

		else

			plane->max_stride = i9xx_plane_max_stride;
@@ -863,17 +863,17 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
		plane->async_flip = g4x_primary_async_flip;

		plane->enable_flip_done = bdw_primary_enable_flip_done;

		plane->disable_flip_done = bdw_primary_disable_flip_done;

	} else if (INTEL_GEN(dev_priv) >= 7) {

	} else if (DISPLAY_VER(dev_priv) >= 7) {

		plane->async_flip = g4x_primary_async_flip;

		plane->enable_flip_done = ivb_primary_enable_flip_done;

		plane->disable_flip_done = ivb_primary_disable_flip_done;

	} else if (INTEL_GEN(dev_priv) >= 5) {

	} else if (DISPLAY_VER(dev_priv) >= 5) {

		plane->async_flip = g4x_primary_async_flip;

		plane->enable_flip_done = ilk_primary_enable_flip_done;

		plane->disable_flip_done = ilk_primary_disable_flip_done;

	}



	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))

	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))

		ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,

					       0, plane_funcs,

					       formats, num_formats,
@@ -895,14 +895,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
		supported_rotations =

			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |

			DRM_MODE_REFLECT_X;

	} else if (INTEL_GEN(dev_priv) >= 4) {

	} else if (DISPLAY_VER(dev_priv) >= 4) {

		supported_rotations =

			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;

	} else {

		supported_rotations = DRM_MODE_ROTATE_0;

	}



	if (INTEL_GEN(dev_priv) >= 4)

	if (DISPLAY_VER(dev_priv) >= 4)

		drm_plane_create_rotation_property(&plane->base,

						   DRM_MODE_ROTATE_0,

						   supported_rotations);
@@ -985,7 +985,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));



	if (INTEL_GEN(dev_priv) >= 4) {

	if (DISPLAY_VER(dev_priv) >= 4) {

		if (val & DISPPLANE_TILED) {

			plane_config->tiling = I915_TILING_X;

			fb->modifier = I915_FORMAT_MOD_X_TILED;
@@ -1006,7 +1006,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));

		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;

	} else if (INTEL_GEN(dev_priv) >= 4) {

	} else if (DISPLAY_VER(dev_priv) >= 4) {

		if (plane_config->tiling)

			offset = intel_de_read(dev_priv,

					       DSPTILEOFF(i9xx_plane));

drivers/gpu/drm/i915/display/icl_dsi.c

+7 −7
Original line number Diff line number Diff line
@@ -457,7 +457,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);



		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */

		if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {

		if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {

			tmp = intel_de_read(dev_priv,

					    ICL_PORT_PCS_DW1_AUX(phy));

			tmp &= ~LATENCY_OPTIM_MASK;
@@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 
	 * a value '0' inside TA_PARAM_REGISTERS otherwise

	 * leave all fields at HW default values.

	 */

	if (IS_GEN(dev_priv, 11)) {

	if (IS_DISPLAY_VER(dev_priv, 11)) {

		if (afe_clk(encoder, crtc_state) <= 800000) {

			for_each_dsi_port(port, intel_dsi->ports) {

				tmp = intel_de_read(dev_priv,
@@ -692,7 +692,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, 
	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);



	for_each_dsi_phy(phy, intel_dsi->phys) {

		if (INTEL_GEN(dev_priv) >= 12)

		if (DISPLAY_VER(dev_priv) >= 12)

			val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

		else

			val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
@@ -774,7 +774,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
			}

		}



		if (INTEL_GEN(dev_priv) >= 12) {

		if (DISPLAY_VER(dev_priv) >= 12) {

			if (is_vid_mode(intel_dsi))

				tmp |= BLANKING_PACKET_ENABLE;

		}
@@ -1020,7 +1020,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	}



	/* program TRANS_VBLANK register, should be same as vtotal programmed */

	if (INTEL_GEN(dev_priv) >= 12) {

	if (DISPLAY_VER(dev_priv) >= 12) {

		for_each_dsi_port(port, intel_dsi->ports) {

			dsi_trans = dsi_port_to_transcoder(port);

			intel_de_write(dev_priv, VBLANK(dsi_trans),
@@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 
	gen11_dsi_configure_transcoder(encoder, crtc_state);



	/* Step 4l: Gate DDI clocks */

	if (IS_GEN(dev_priv, 11))

	if (IS_DISPLAY_VER(dev_priv, 11))

		gen11_dsi_gate_clocks(encoder);

}
@@ -1534,7 +1534,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;

	int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;

	bool use_dsc;

	int ret;

drivers/gpu/drm/i915/display/intel_atomic.c

+3 −3
Original line number Diff line number Diff line
@@ -332,7 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
	    plane_state->hw.fb->format->is_yuv &&

	    plane_state->hw.fb->format->num_planes > 1) {

		struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

		if (IS_GEN(dev_priv, 9) &&

		if (IS_DISPLAY_VER(dev_priv, 9) &&

		    !IS_GEMINILAKE(dev_priv)) {

			mode = SKL_PS_SCALER_MODE_NV12;

		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
@@ -351,7 +351,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
			if (linked)

				mode |= PS_PLANE_Y_SEL(linked->id);

		}

	} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {

	} else if (DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {

		mode = PS_SCALER_MODE_NORMAL;

	} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {

		/*
@@ -460,7 +460,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 
				 * isn't necessary to change between HQ and dyn mode

				 * on those platforms.

				 */

				if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

				if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

					continue;



				plane = drm_plane_from_index(&dev_priv->drm, i);

drivers/gpu/drm/i915/display/intel_audio.c

+9 −9
Original line number Diff line number Diff line
@@ -248,7 +248,7 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta 
			break;

	}



	if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)

	if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)

		i = ARRAY_SIZE(hdmi_audio_clock);



	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
@@ -586,14 +586,14 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder, 
	unsigned int hblank_early_prog, samples_room;

	unsigned int val;



	if (INTEL_GEN(i915) < 11)

	if (DISPLAY_VER(i915) < 11)

		return;



	val = intel_de_read(i915, AUD_CONFIG_BE);



	if (INTEL_GEN(i915) == 11)

	if (IS_DISPLAY_VER(i915, 11))

		val |= HBLANK_EARLY_ENABLE_ICL(pipe);

	else if (INTEL_GEN(i915) >= 12)

	else if (DISPLAY_VER(i915) >= 12)

		val |= HBLANK_EARLY_ENABLE_TGL(pipe);



	if (crtc_state->dsc.compression_enable &&
@@ -933,7 +933,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;

		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;

	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {

	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {

		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;

		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;

	} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -1010,7 +1010,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 
	ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);



	if (dev_priv->audio_power_refcount++ == 0) {

		if (INTEL_GEN(dev_priv) >= 9) {

		if (DISPLAY_VER(dev_priv) >= 9) {

			intel_de_write(dev_priv, AUD_FREQ_CNTRL,

				       dev_priv->audio_freq_cntrl);

			drm_dbg_kms(&dev_priv->drm,
@@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) 
		if (IS_GEMINILAKE(dev_priv))

			glk_force_audio_cdclk(dev_priv, true);



		if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

		if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))

			intel_de_write(dev_priv, AUD_PIN_BUF_CTL,

				       (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));

	}
@@ -1050,7 +1050,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, 
	unsigned long cookie;

	u32 tmp;



	if (INTEL_GEN(dev_priv) < 9)

	if (DISPLAY_VER(dev_priv) < 9)

		return;



	cookie = i915_audio_component_get_power(kdev);
@@ -1296,7 +1296,7 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) 
		return;

	}



	if (INTEL_GEN(dev_priv) >= 9) {

	if (DISPLAY_VER(dev_priv) >= 9) {

		dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,

							   AUD_FREQ_CNTRL);

		drm_dbg_kms(&dev_priv->drm,

drivers/gpu/drm/i915/display/intel_bios.c

+7 −7
Original line number Diff line number Diff line
@@ -544,7 +544,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915, 
static int intel_bios_ssc_frequency(struct drm_i915_private *i915,

				    bool alternate)

{

	switch (INTEL_GEN(i915)) {

	switch (DISPLAY_VER(i915)) {

	case 2:

		return alternate ? 66667 : 48000;

	case 3:
@@ -610,7 +610,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915) 
	 * Only parse SDVO mappings on gens that could have SDVO. This isn't

	 * accurate and doesn't have to be, as long as it's not too strict.

	 */

	if (!IS_GEN_RANGE(i915, 3, 7)) {

	if (!IS_DISPLAY_RANGE(i915, 3, 7)) {

		drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n");

		return;

	}
@@ -684,7 +684,7 @@ parse_driver_features(struct drm_i915_private *i915, 
	if (!driver)

		return;



	if (INTEL_GEN(i915) >= 5) {

	if (DISPLAY_VER(i915) >= 5) {

		/*

		 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS

		 * to mean "eDP". The VBT spec doesn't agree with that
@@ -918,7 +918,7 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 
	 */

	if (bdb->version >= 205 &&

	    (IS_GEN9_BC(i915) || IS_GEMINILAKE(i915) ||

	     INTEL_GEN(i915) >= 10)) {

	     DISPLAY_VER(i915) >= 10)) {

		switch (psr_table->tp1_wakeup_time) {

		case 0:

			i915->vbt.psr.tp1_wakeup_time_us = 500;
@@ -1806,7 +1806,7 @@ static void sanitize_device_type(struct intel_bios_encoder_data *devdata, 
	struct drm_i915_private *i915 = devdata->i915;

	bool is_hdmi;



	if (port != PORT_A || INTEL_GEN(i915) >= 12)

	if (port != PORT_A || DISPLAY_VER(i915) >= 12)

		return;



	if (!(devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING))
@@ -2647,8 +2647,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *i915, 
		dvo_port = child->dvo_port;



		if (dvo_port == DVO_PORT_MIPIA ||

		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(i915) >= 11) ||

		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(i915) < 11)) {

		    (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) ||

		    (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) {

			if (port)

				*port = dvo_port - DVO_PORT_MIPIA;

			return true;